FPGA Implementation of Low Power Booth Multiplier Using Radix-4 Algorithm

As the scale of integration keeps growing, more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amounts of energy. While performance and area remain to be two major design goals, power consumption has become a critical concern in today’s VLSI system design. Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power.

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International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE)