International Journal of Computer Science and Telecommunications
Modular multiplication is a key operation in public key cryptosystems like RSA. Among modular multiplication methods, montgomery modular multiplication is an efficient algorithm suitable for hardware implementation. In this paper, a modified montgomery modular multiplication design is proposed with carry save adder architecture and parallel simplified quotient computation for the next iteration. The proposed design has a high clock frequency and high throughput. The proposed design and RSA are implemented on Virtex 2 and Virtex 5 FPGAs.