FPGA Implementation of Novel High Speed Vedic Multiplier

Provided by: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE)
Topic: Hardware
Format: PDF
Now-a-days, almost all DSP and communication applications require high speed processors. The speed of a processor is mainly given in terms of performance of ALU and in turn in terms of MAC unit. MAC (Multiplier and ACcumulator unit) is the main arithmetic processing unit of ALU. The demand for high speed processing necessitates high speed multiplier architecture. In this paper, a novel high speed 8-bit Vedic multiplier is proposed using the ancient Indian Vedic mathematics technique. It uses four 4x4 multipliers designed using Urdhwa Tiryagbhyam sutra for partial product generation.

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