FPGA Implementation of Optimized Decimation Filter for Wireless Communication Receivers

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Provided by: The International Journal of Innovative Research in Computer and Communication Engineering
Topic: Hardware
Format: PDF
Digital Down Converter (DDC) is very important and integral part of the multi-rate wireless communication system. As it utilizes the major resources, therefore its low cost and efficient implementation is of main concern. This paper presents and implements a FPGA based optimized design of decimation filter for wireless communication receivers. Cascaded Integrated Comb (CIC) filters are multiplier less linear filters which are extensively used in multi-rate systems for the purpose of Digital Down Conversion (DDC). An optimized architecture based upon these filters is analyzed and implemented.
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