FPGA Implementation of Optimized the 64-Bit RC5 Encryption Algorithm
In this paper, the author presents a FPGA based the 64-bit RC5 encryption algorithm. One of complex operation in RC5 encryption is rotate thus they implementation this operation on FPGA using barrel shifter. They implement total of mathematic equations based optimized logic circuits until dynamic power consumption reduced, also for increase in speed and maximum operation frequency they using pipelining technique in proposed method. The results from the place and route report indicate that logic utilization by this architecture is 17% with a maximum clock frequency of 175.69 MHz.