FPGA Implementation of Phase Locked Loop (PLL) with Synchronous Reset

Provided by: Institute of Research and Journals (IRAJ)
Topic: Hardware
Format: PDF
Modern high frequency, high performance System-on-Chip (SoC) design is heading to include more and more analog or mixed signal circuits as well as digital blocks. As the complexity of a system grows, it becomes more and more important to implement the system simulation and top-down design methodology as well. In this paper, the authors have designed a phase locked loop using Verilog and Xilinx. Considering the rapid growth in computer automation and computer networking sector, FPGA implementation technique of PLL has been adopted in this paper.

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