Initially, SEA is designed for software implementations in controllers, smart cards, or processors. In this paper, the authors proposed a system that investigates its performances in recent Field-Programmable Gate Array (FPGA) devices. The present symmetric encryption algorithms result from a tradeoff between implementation cost and resulting performances. The proposed system is applicable where there are limited processing resources with high throughput requirements. For this purpose, they propose SEA loop architecture with behavior model Verilog HDL coding.