FPGA Implementation of Ternary Pulse Compression Sequences with Superior Merit Factors

Provided by: NORTH ATLANTIC UNIVERSITY UNION
Topic: Hardware
Format: PDF
Ternary codes have been widely used in radar and communication areas, but the synthesis of ternary codes with good merit factor is a non-linear multivariable optimization problem, which is usually difficult to tackle. To get the solution of above problem many global optimization algorithms like genetic algorithm, simulated annealing and tunneling algorithm were reported in the paper. However, there is no guarantee to get global optimum point. In this paper, a novel and efficient VLSI architecture is proposed to design ternary pulse compression sequences with good merit factor.

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