FPGA Implementation of Variable-Latency Speculating Booth Multiplier (VLSBM)

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
Data hazards cause major pipeline performance degradation for data-intensive computing processes. To improve the performance of the pipeline efficiency, a high-speed VLSBM is proposed. This is done by successively performing a speculating and correcting phase. To decrease the critical path, the VLSBM partial products are divided into the (n - z) bit Least Significant Part (LSP) and the (n + z) bit Most Significant Part (MSP). The estimation function predicts the carry to the MSP, thereby permitting independent calculation of the partial-product accumulation of parts.
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