FPGA Implementations of Low Precision Floating Point Multiply-Accumulate

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Provided by: Liferay
Topic: Hardware
Format: PDF
Floating Point (FP) Multiply-ACcumulate (MAC) represents one of the most important operations in a wide range of applications, such as DSP, multimedia or graphic processing. This paper presents a FP MAC half precision (16-bit) FPGA implementation. The main contribution of this work is represented by the utilization of modern FPGA DSP block for performing both mantissa multiplication and mantissa accumulation. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on one of the multiplicand, and, a left shift for the other.
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