FPGA Optimized Packet-Switched NoC using Split and Merge Primitives

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Due to their different cost structures, the architecture of switches for an FPGA packet-switched Network-on-Chip (NoC) should differ from their ASIC counterparts. The CONNECT network recently demonstrated several ways in which packet-switched FPGA NoCs should differ from ASIC NoCs. However, they also concluded that pipelining was not appropriate for the FPGA switches. The authors show that the Split-Merge switch architecture is more amenable to pipelining on FPGAs, achieving 300MHz operation - up to three times the frequency and throughput of the CONNECT switches - with only 13 - 37% more area.

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