Institute of Electrical & Electronic Engineers
Last Level Caches (LLCs) account for a substantial fraction of the area and power budget in many modern processors. Two recent trends - dwindling die yield that falls off sharply with larger chips and increasing static power - make a strong case for a fresh look at LLC design. Inclusive caches are particularly interesting because many commercially successful processors use inclusion to ease coherence at a cost of some data being stale or redundant. This paper have demonstrated that LLC designs could be improved through static or dynamic use of \"Dataless ways\".