From High Level MPSoC Description to SystemC Code Generation

Provided by: INRIA
Topic: Hardware
Format: PDF
In this paper, the authors present an efficient Multi-Processor Systems-on-Chip (MPSoC) design flow. It is based on a Model-Driven Engineering (MDE) approach. A compilation chain has been developed to transform the high abstraction level into both Cycle Accurate Bit Accurate (CABA) and Timed Programmer View PVT SystemC simulation. They use the standard MARTE profile to represent MPSoC systems. This paper separates the application, the hardware architecture and the corresponding allocation. Later, through several model to model transformations, they succeed to generate SystemC code of the modeled MPSoC system.

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