International Journal of Engineering Research and Applications (IJERA)
The design of a power and area efficient high speed 768 000-bit multiplier based on Fast Fourier Transform (FFT) multiplication for fully homomorphic encryption operations. Memory based in-place architecture is presented for the FFT processor that performs 64 000-point finite-field FFT operations using a radix-16 computing unit and 16 dual-port SRAMs. By adopting a special prime as the base of the finite field, the radix-16 calculations are simplified to requiring only additions and shift operations. A two-stage carry-look-ahead scheme is employed to resolve carries and obtain the multiplication result.