Functional and Timing Validation of Partially Bypassed Processor Pipelines

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Provided by: edaa
Topic: Hardware
Format: PDF
Customizing the bypasses in pipelined processors is an effective and popular means to perform power, performance and complexity trade-offs in embedded systems. However existing techniques are unable to automatically generate test patterns to functionally validate a partially bypassed processor. Manually specifying directed test sequences to validate a partially bypassed processor is not only a complex and cumbersome task, but is also highly error-prone. In this paper the authors present an automatic directed test generation technique to verify a partially bypassed processor pipeline using a high-level processor description.
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