Institute of Electrical & Electronic Engineers
Modern semiconductor industry faces severe scaling problems while attempting to keep pace with Moore's Law. In particular, one of the major challenges is the increasing communication delay due to long interconnect wires. The emerging Through Silicon Via (TSV) based 3D integration technology provides the means to stack two or more dies, enabling a low-latency interface between them. Apart of the immediate advantages of such an approach, e.g., short wires, it also opens research avenues for 3D organizations of computation platforms. In this paper, the authors propose to share resources between stacked processors while focusing on Functional Units (FUs) inter-die sharing.