Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction

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Provided by: Imperial College London
Topic: Hardware
Format: PDF
To complement the flexible, fine-grain logic in Field Programmable Gate Arrays (FPGAs), configurable hardware devices now incorporate more complex coarse-grain components such as memories, embedded processing units and fused arithmetic units. These components provide speed and density advantages due to the specialized logic and fixed interconnect. In this paper, a methodology is presented to automatically propose and explore the benefits of different types of fused arithmetic units for configurable devices. The methods are based on common subgraph extraction techniques, meaning that it is possible to explore different subcircuits that occur frequently across a set of benchmarks.
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