Gate Leakage Aware Optimal Design of Modified Hybrid Nanoscale MOSFET and Its Application to Logic Circuits
With the explosive growth in portable computing and wireless communication during last few years, power dissipation has become critical issue. Under such condition gate leakage has been recognized as a dominant component of power dissipation. This paper proposes a Modified Hybrid MOSFET (MHMOSFET) i.e. gate-to-source/drain non-overlap MOSFET in combination with high-k layer/interfacial oxide as gate stack to reduce the gate leakage current. Compact analytical model and Sentaurus simulation have been used to study the gate leakage behavior of MHMOS.