Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic
A digital clock has been designed at gate level and is being presented in this paper. The clock architecture consists of three major blocks second, minute and hour. The architecture is the amalgam both of synchronous and asynchronous logic. All the flip-flops at each block run synchronously. The triggering operation of a block is asynchronous in nature. It serves the design requiring lower power consumption, provides lesser noise and electromagnetic interference, lower delay and greater throughput. The clock is designed at Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and Simulated by Vegilogger Pro 6.5.