Gate Sizing for Large Cell-Based Designs

Provided by: edaa
Topic: Hardware
Format: PDF
Today, many chips are designed with predefined discrete cell libraries. In this paper the authors present a new fast gate sizing algorithm that works natively with discrete cell choices and realistic timing models. The approach iteratively assigns signal slew targets to all source pins of the chip and chooses discrete layouts of minimum size preserving the slew targets. Using slew targets instead of delay budgets, accurate estimates for the input slews are available during the sizing step.

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