Since there is many advancement in VLSI technology and there are many efficient styles of designing VLSI circuits. Some of the styles are CMOS, PTL, GDI (Gate Diffusion Input) techniques. GDI technique helps in designing low-power digital combinatorial circuit by which the authors can eradicate demerits of CMOS, PTL techniques. This paper allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. The different methods are compared with respect to the layout area; transistor count, delay, and power dissipation are discussed here in this paper, showing advantages and drawbacks of GDI compared to CMOS style.