International Journal of Scientific & Engineering Research
In this paper, the authors propose design of six stage pipelined processor. The architecture is modified to increase the speed of operation. The architecture of the processor includes the ALU, pipelined data-path, data forwarding unit, control logic, data and program memories and hazard control unit. Hazard detection unit and data forwarding unit have been included for efficient implementation of the pipeline. Design and verification of processor has been done using Verilog on Xilinx 14.1 platform and assembler is written in PERL language which decrease the complexity of instruction writing in program memory is used in this design.