Generating Finite State Machines from SystemC
SystemC is a system level language proposed to raise the abstraction level for embedded systems design and verification. In this paper, the authors propose to generate Finite State Machines (FSM) from SystemC designs using two algorithms originally proposed for the generation of FSM from Abstract State Machines (ASM). This proposal enables the integration of SystemC with existing tools for test case generation from FSM. Hence, enabling two important applications: using the FSM graph structure to produce test suites allowing functional testing of SystemC designs and performing conformance testing, where the FSM serves as a precise model of the observable behavior of the system used to validate lower abstraction levels of the design (e.g., Register Transfer Level (RTL)).