Glitch-Aware Output Switching Activity From Word-Level Statistics

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Provided by: Imperial College London
Topic: Hardware
Format: PDF
In this paper, the author's present models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures of the correlation and variance of the input signals to these components. This will allow the power consumed in the output wires of these components to be estimated from a high-level description before RTL-synthesis, without resorting to time-consuming low-level simulation. The proposed model combines knowledge of the internal construction of adders on FPGAs with the transition density model for activity propagation and typical activity profiles for signals within Digital Signal Processing (DSP) systems according to the DBT model, and is characterized using device-level power measurements.
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