Glitch Power Minimization Techniques in Low Power VLSI Circuits

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Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Topic: Hardware
Format: PDF
Due to miniaturization of circuit mobility degradation, velocity saturation and power dissipation issues are critical in the design of VLSI circuits. In this paper, various techniques to minimize power dissipation due to glitches are discussed. Total power consumption consists of two major parts like static power consumption and dynamic power consumption. In the total power, the static power is 30% and dynamic power is 70%. The power due to glitches is 70% of the dynamic power and 30% of the total power.
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