Institute of Electrical & Electronic Engineers
Heterogeneous or co-processor architectures are becoming an important component of High Productivity Computing Systems (HPCS). In this work the performance of a GPU based HPCS is compared with the performance of a commercially available FPGA based HPC. Contrary to previous approaches that focused on specific examples, a broader analysis is performed by considering processes at an architectural level. A set of benchmarks is employed that use different process architectures in order to exploit the benefits of each technology. These include the asynchronous pipelines common to \"Map\" tasks, a partially synchronous tree common to \"Reduce\" tasks and a fully synchronous, fully connected mesh.