GROK-INT: Generating Real On-chip Knowledge for Interconnect Delays Using Timing Extraction

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
With continued scaling, all transistors are no longer created equal. The delay of a length 4 horizontal routing segment at coordinates (23,17) will differ from one at (12,14) in the same FPGA and from the same segment in another FPGA. The vendor tools give conservative values for these delays, but knowing exactly what these delays are can be invaluable. In this paper, the authors show how to obtain this information, inexpensively, using only components that already exist on the FPGA (configurable PLLs, registers, logic, and interconnect). The techniques, they present are general and can be used to measure the delays of any resource on any FPGA with these components.
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