GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Timing extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the ne-grained delays allows a detailed understanding of the amount and type of process variation that exists in the FPGA. To obtain these delays, timing extraction measures, using only resources already available in the FPGA, the de-lay of a small subset of the total paths in the FPGA.

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