GUI Based Complex Test Pattern Generation for High Speed Fault Diagnosis in Memory Chips

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Provided by: International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE)
Topic: Hardware
Format: PDF
The memory blocks testing is a separate testing procedure followed in VLSI testing. The memory blocks testing involve writing a specific bit sequences in the memory locations and reading them again. This type of test is called March test. A particular March test consists of a sequence of writes followed by reads with increasing or decreasing address. For example the March C- test has the following test pattern. There are several test circuits available for testing the memory chips. However no test setup is developed so far for testing the memory blocks inside the FPGA.
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