Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers

Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
Modern microprocessors increasingly integrate the Memory Controller (MC) on-chip in order to reduce main memory access latency. Memory pressure will increase with increasing core-counts per socket and a single MC will quickly be-come a bottleneck. In order to avoid this problem, modern multi-core processors (Chip Multi-Processors, CMPs) have be-gun to integrate multiple MCs per socket. Similarly, multi-socket motherboards provide connections to multiple MCs via o -chip interconnects such as AMD's Hyper-Transport (HT) and Intel's Quick Path Interconnect (QPI). In both architectures, a core may access any DRAM location by routing its request to the appropriate MC.

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