Hardware Algorithm for Variable Precision Multiplication on FPGA

Provided by: International Journal of Engineering Research and Development (IJERD)
Topic: Hardware
Format: PDF
A hardwired algorithm for computing the variable precision multiplication is presented in this paper. The computation method is based on the use of a parallel multiplier of size m to compute the multiplication of two numbers of nxm bits. These numbers are represented in the variable precision floating point format, but in this paper, only the mantissas are considered; the exponents are easily obtained by adding the exponents of the two operands to be multiplied. In this computing method of multiplication, the partial products are added as soon as they are computed, resulting in the use of the lowest memory for intermediate results storage, (i.e. the size of the result is of 2nxm bits).

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