Hardware Description of Digital Adaptive IIR Filters for Implementing on FPGA
The hardware description and implementation of adaptive Infinite-Impulse-Response (IIR) filters for real-time applications is an important and challenging designing issue. This paper is hardware description of digital adaptive IIR filters for implementing on Field Programmable Gate Array (FPGA) chips. The direct architecture is considered for IIR filter designing and Equation-Error (EE) Least Mean Square (LMS) adaptive algorithm is employed for updating filter coefficients. Adaptive IIR filter is employed in interference cancellation and inverse system identification applications and the results are compared with Finite-Impulse Response (FIR) filter in terms of convergence speed, maximum operating frequency, chip area and power dissipation criteria.