Hardware Efficient Multiplier Using Resource Reuse

In this paper, the authors proposed an area efficient low power multiplier using resource reuse technique. The proposed design uses efficient design of half and full adder circuits which uses less number of logic gates. As the binary multipliers for nxn bits requires n rows of adder circuit to manipulate the product term. The proposed design requires only 3 rows of adders and intermediate product terms are stored in the memory elements (flip-flop).

Resource Details

Provided by:
International Journal of Modern Engineering and Research Technology (IJMERT)