Hardware Efficient Piecewise Linear Branch Predictor

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Provided by: University of Texas at Arlington
Topic: Hardware
Format: PDF
Piecewise linear branch predictor has been demonstrated to have superior prediction accuracy; however, its huge hardware overhead prevents the predictor from being practical in the VLSI design. This paper presents two novel techniques targeting at reducing the hardware cost of the predictor, i.e., history skewed indexing and stack-based misprediction recovery. The former is designed to reduce the number of ahead-pipelined paths by introducing the history bits in the index of the weight table, while the latter employs stacks instead of arrays of registers to recover predictor states from misprediction.
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