Hardware Efficient Reconfigurable Arithmetic Unit

Various applications, e.g. commercial and financial electronic transactions, internet and industrial control require precise arithmetic for different data representation formats. In this paper, the authors present an arithmetic unit which performs addition and subtraction on Binary & binary Coded Decimal (BCD) numbers. The unit is able to perform effective addition-subtraction operations on unsigned, signed magnitude and various complement representations. The design is runtime reconfigurable and all the subunits have been designed to work with least delay. The proposed unit is synthesized for 4vfx60ff672-12 Xilinx Virtex-4 FPGA.

Provided by: Institute of Research Engineers and Doctors Topic: Hardware Date Added: May 2012 Format: PDF

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