Hardware Implementation of AES Encryption and Decryption for Low Area & Low Power Consumption

Provided by: International Journal of Ethics in Engineering & Management Education (IJEEE)
Topic: Security
Format: PDF
In this paper, the authors are to code a data encryption system using Advanced Encryption Standard (AES) algorithm in Hardware Description Language (HDL), and to test it according to a predetermined standard stimulus so that it meets requirements. An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. They achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.

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