Hardware Implementation of Decimation in Time FFT

Provided by: MIT Publications
Topic: Hardware
Format: PDF
The Fast Fourier Transform (FFT) is an indispensable operation in many digital signal processing applications but yet is deemed computationally expensive when performed on a conventional general purpose processors. This paper explains the implementation of radix-22 single-path delay feedback pipelined DIT- FFT processor. This architecture has the same multiplicative complexity as radix-4 algorithm, but retains the simple butterfly structure of radix-2 algorithm. The implementation was made on a Field Programmable Gate Array (FPGA) because it can achieve higher computing speed than digital signal processors, and also can achieve cost effectively ASIC-like performance with lower development time, and risks.

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