University of Waterloo
Hardware implementation of the main building block (compression function) for five different SHA-3 candidates is presented. The five candidates, namely Blue Midnight Wish, Luffa, Skein, Shabal and Blake have been considered since they present faster software implementation results compared to the rest of the SHA-3 proposals. The compression functions realized in hardware create the message digest of size 256 bits. The authors report both ASIC (Application-Specific Integrated Circuit) and FPGA (Field-Programmable Gate Array) implementations. The results allow an easy comparison for hardware performance of the candidates.