Hardware Realization of FIR Filter Implementation through FPGA

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
Distributed Arithmetic (DA) is an important technique to implement Digital Signal Processing (DSP) functions in FPGA. It is a powerful technique for reducing the size of a parallel hardware. When DA (Distributed Arithmetic) algorithm is directly applied to the FPGA (Field Programmable Gate Array) to realize FIR (Finite Impulse Response) filter, it is difficult to achieve the best configuration in the coefficient of FIR filter, the storage resource and the computing speed. According to this problem, the paper provides the detailed analysis and discussion in the algorithm, the memory size and look-up table speed.
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