Hardware/Software Optimization of Error Detection Implementation for Real-Time Embedded Systems

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
In this paper the authors present an approach to system-level optimization of error detection implementation in the context of fault-tolerant real-time distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Their main focus in this paper is on the efficient implementation of the error detection mechanisms.
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