Hardware Support for CSP on a Java Chip Multiprocessor

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Provided by: Reed Business Information
Topic: Hardware
Format: PDF
Due to memory bandwidth limitations, Chip Multi-Processors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem that can lead to further performance increase for a number of multithreaded applications. Programmatically, the Communicating Sequential Processes (CSPs) paradigm provides a sound computational model for such an architecture with message based communication. In this paper, the authors explore hardware support for CSP in the context of an embedded java CMP.
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