Georgia Institute of Technology
The aggressive evolution of the semiconductor industry smaller process geometries, higher densities, and greater chip complexity has provided design engineers the means to create complex, high-performance Systems-on-Chip (SoC) designs. Such, SoC designs typically have more than one processor and huge memory, all on the same chip. Dealing with the global on-chip memory allocation/de-allocation in a dynamic yet deterministic way is an important issue for the upcoming billion transistor multiprocessor SoC designs. To achieve this, the authors propose a memory management hierarchy they call two-level memory management.