Hazard Driven Test Generation for SMT Processors

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Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
Multithreaded processors increase throughput by executing multiple independent programs on a single pipeline. Simultaneous Multi-Threaded (SMT) processors execute multiple threads simultaneously thus add a significant dimension to the design complexity. Dealing with this complexity calls for extended and innovative design verification efforts. This paper develops an analytic model based SMT random test generation technique. SMT analytic model parameters are applied to create random tests with high utilization and increased contention. To demonstrate the methodology, parameters extracted from the PPC ISA and sample processor configurations are simulated on the SMT analytic model.
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