Provided by: International Journal of Computer Applications
Date Added: Sep 2014
In this paper, the authors aim the designing and implementing an efficient HDLC chip. They use pipelining technique in HDLC register module which increases the throughput of the system and also helps in decreasing the delay of the system. In pipeline technique, number of instructions has been executed at the same time. The HDLC chip designed here supports two way communications means it supports full duplex communications which means that it can transmit and receive continuously. In this paper, they adopt Xilinx's Spartan-3E for HDLC implementation and for hardware simulation they use Modelsim SE 6.2C.