HELIX: Automatic Parallelization of Irregular Programs for Chip Multiprocessing

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Provided by: University of California, Santa Cruz
Topic: Hardware
Format: PDF
The authors describe and evaluate HELIX, a new technique for automatic loop parallelization that assigns successive iterations of a loop to separate threads. They show that the inter-thread communication costs forced by loop-carried data dependences can be mitigated by code optimization, by using an effective heuristic for selecting loops to parallelize, and by using helper threads to prefetch synchronization signals. They have implemented HELIX as part of an optimizing compiler framework that automatically selects and parallelizes loops from general sequential programs.
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