Institute of Electrical & Electronic Engineers
Hybrid nanophotonic-electric Network-on-Chips (NoCs) have been recently proposed to overcome the challenges of high data transfer latencies and significant power dissipation in traditional electrical NoCs. But hybrid NoCs with nanophotonic guided waveguides and silicon microring resonator modulators impose many challenges such as high thermal tune up power and crossing losses. Due to these challenges productization of such architectures has yet to become commercially viable. Unfortunately, increasing embedded application complexity, hardware dependencies, and performance variability makes optimizing hybrid NoCs a daunting task because of the need to explore a massive design space at the system-level.