Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
The evolution of deep submicron technologies allows the development of increasingly complex System-on-Chip (SoC). However, this evolution is rendering less viable some well-established design practices. Examples are the use of multi-point communication architectures (e. g. busses) and designing fully synchronous systems. In addition, power dissipation is becoming one of the main design concerns due e. g. to the increasing use of mobile products. An alternative to overcome such problems is adopting Network-on-Chips (NoCs) communication architectures supporting Globally Asynchronous Locally Synchronous (GALS) system design.
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