Heterogeneous Die Stacking of SRAM Row Cache and 3D DRAM: An Empirical Design Evaluation

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Provided by: Georgia Institute of Technology
Topic: Storage
Format: PDF
As DRAM scaling becomes more challenging and its energy efficiency receives a growing concern for data center operation, an alternative approach - stacking DRAM die with Thru-Silicon Vias (TSV) using 3-D integration technology is being undertaken by industry to address these looming issues. Furthermore, 3-D technology also enables heterogeneous die stacking within one DRAM package. In this paper, the authors study how to design such a heterogeneous DRAM chip for improving both performance and energy efficiency, in particular, They propose a novel floorplan and several architectural techniques to fully exploit the benefits of 3-D die stacking technology when integrating an SRAM row cache into a DRAM chip.
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