Delft University of Technology
In this paper, the authors present an overview of interconnect solutions for hardware accelerator systems. A number of solutions are presented: bus-based, DMA, crossbar, NoC, as well as combinations of these. The paper proposes analytical models to predict the performance of these solutions and implements them in practice. The jpeg decoder application is implemented as their case study in different scenarios using the presented interconnects solutions. They profile the application to extract the input data for their analytical model. Measurement results show that the NoC solution combined with a bus-based system provides the best performance as predicted by the analytical models.