Institute of Electrical & Electronic Engineers
A novel heterogeneously encoded dual-bit self-timed adder design is presented in this paper. Heterogeneous encoding refers to a combination of at least two different delay-insensitive encoding schemes, adopted for the inputs and outputs. The primary motivation being that higher order 1-of-n encoding protocols facilitate reduction in terms of the circuit switching power dissipation compared to the basic dual-rail (1-of-2, which is the simplest 1-of-n code) encoding scheme. Here, n specifies the number of physical lines. The number of transitions gets reduced by O (k) over a dual-rail code, with k being the number of primary inputs and equals log2n.